Razor: a low-power pipeline based on circuit-level timing speculation
From AcaWiki
Citation: Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, Trevor Mudge (2004/01/08) Razor: a low-power pipeline based on circuit-level timing speculation. International Symposium on Microarchitecture (RSS)
DOI (original publisher): 10.1109/MICRO.2003.1253179
Semantic Scholar (metadata): 10.1109/MICRO.2003.1253179
Sci-Hub (fulltext): 10.1109/MICRO.2003.1253179
Internet Archive Scholar (search for fulltext): Razor: a low-power pipeline based on circuit-level timing speculation
Download: https://ieeexplore.ieee.org/abstract/document/1253179/
Tagged: Computer Science
(RSS) computer architecture (RSS)
Summary
Placeholder
