Open Source Semiconductor Core Licensing
Author says revenue for semiconductor core designs "was estimated at nearly $1.4 billion in 2007, up from $140 million in 1998 thus growing at approximately twice the rate of the chip industry as a whole", abetted by contract manufacturers and fabless designers.
Core design goes through several stages:
- hardware description language (HDL): very much like software
- logic synthesis: HDL is converted by electronic design automation software into a "netlist": akin to compiled software, allows for simulation and creation of blueprints for device, but not understandable/modifiable by humans
- physical design: creation of manufacture-able blueprint, includes sub-stages:
- floor planning: groups of components are assigned to different areas of the device
- place and route: placement of all components on the device and the connection of these components
- these often involve several iterations, often outsourced, also including mapping power and timing; result is a GDSII file, a graphic format that specifies the complete layout of the final chip design provided to a foundry for the actual physical fabrication of the chip.
Cores may be licensed at different stages. Soft core usually means HDL, sometimes netlist. Hard core means GDSII.
Provisions of the GNU General Public License (GPL) are considered with regard to semicondutor core design licensing:
- "Conveying" a work triggers the GPL requirement to make the work's source available under the GPL, but the scope of conveyance is open for interpretation, e.g., is a copy to an independent offsite contractor/outsourcer a private copy, or distribution? This is pertinent, as a fabless designer will use many contractors. Author speculates full assignment of rights from contractor enhance "private copy" nature of such activities.
- When a work is based on, typically seen as a derivative of, a GPL work, the GPL's copyleft provision is triggered. Distinguishing derivative from compilation is subject to interpretation; author considers "hard" and "soft" core, and "library" cases:
- To what degree does incorporation of GPL "hard core" design influence overall chip design? Is there a blank in the design which an IO (example used) core may be plugged in? If so, the rest of the design may not need to be GPL, but if there is any degree of influence, interpretation is needed. LGPL designs for subcomponents would be more clearly isolated.
- The flexibility offered and work required to turn a "soft core" into a "hard" design make it likely incorporating a GPL soft core would make a larger design based on that GPL work. Author says some isolation could be achieved by only using LGPL soft core designs, and "hardening" design of subcomponent based on GPL soft core design separate from the rest of the design, rendering the analysis same as previous.
- Proprietary EDA tools "use libraries that describe the actual components that will be used in the actual fabrication process" under terms that would conflict with the GPL, making it impossible to use both. Again use of only LGPL designs may mitigate. Further analysis could show that proprietary libraries could satisfy "system library" GPL exception in some cases.
- Author argues that contrary to a FSF FAQ, physical distribution of an object based on a GPL design could trigger requirements to distribute the object's design under the GPL:
- GPL may be seen as a contract, and it is typical for commercial contracts for designs to reach well beyond what copyright restricts
- Even under copyright, courts have held that physical things can be derivatives of designs, for example buildings/architecture
- GPL expressly includes other copyright-like rights; these could extend GPL conditions to physical device distribution
Author concludes "The development of a context-specific open source license may be the simplest way to clarify the applicable legal rules and encourage the commercial use of open source cores."